For example, as the method for realizing high processing performance by using the plurality of general-purpose processors or the plurality of dedicated processors, there is a technique for integrating many general-purpose processors having high processing performance. As such a technique, for example, a network chip mounting eighty pieces of processing engines (PE) is described in Non-Patent Document 1 (S. Vangal, and other thirteen, “An 80-Tile 1.28 TFLOPS Network-on-Chip in 65 nm CMOS”, 2007 IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2007, p. 98-99) and Non-Patent Document 2 (S. Vangal, and other fourteen, “An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, January 2008, p. 29-41). As one example, the network chip described in Non-Patent Document 2 operates at a power supply voltage of 1.07 V and a clock frequency of 4.27 GHz, and it provides processing performance of 1.0 TFLOPS with a power consumption of 97 W.
Also, Patent Document 1 (Japanese Patent Application Laid-Open publication No. 2006-39623) discloses a microcontroller which has a CPU section, a memory section, and a power supplying section supplying power supply voltage individually to circuit blocks such as a peripheral circuit, and which can vary the voltage supplied individually to the circuit blocks.